A system on a programmable chip (SOPC) includes one or more integrated circuits that may be programmed to perform one or more logic functions. One type of SOPC may be implemented using a Field Programmable Gate Array (FPGA). The FPGA may include an array of logic blocks. These logic blocks can include, for example, input/output Blocks, Random Access Memory Blocks (BRAMs), multipliers, Digital Signal Processing blocks (DSPs), processors, clock managers, Delay Lock Loops (DLLs), Multi-Gigabit Transceivers (MGTs), and so forth.
Each logic block typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by Programmable Interconnect Points (PIPs). The programmable interconnect and the programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the logic blocks are configured. The configuration data may be read from a configuration memory, such as an external programmable read-only memory (PROM) or external Flash memory. The collective states of the individual memory cells then determine the function of the FPGA.
As FPGAs grow in size and capability, the amount of configuration memory used to configure the logic blocks also increases. This configuration memory may be expensive and may also require additional space on a board on which the SOPC is implemented. For example, the Flash memory may be costly and also may consume a large amount of board area.